The present invention relates to a display apparatus, and particularly to a dot-sequential driving active matrix display apparatus using a so-called non-overlap sampling method for a horizontal driving circuit thereof.
In a display apparatus, for example an active matrix liquid crystal display apparatus using a liquid crystal cell as a display element (electro-optical element) of a pixel, a horizontal driving circuit of a dot-sequential driving type using a clock driving method, for example, is known. FIG. 8 shows a conventional example of the clock driving type horizontal driving circuit. In FIG. 8, the horizontal driving circuit 100 has a shift register 101, a clock extracting switch group 102, and a sampling switch group 103.
The shift register 101 includes n shift stages (transfer stages). When a horizontal start pulse HST is supplied to the shift register 101, the shift register 101 performs shift operation in synchronism with horizontal clocks HCK and HCKX opposite to each other in phase. Thereby, as shown in a timing chart of FIG. 9, the shift stages of the shift register 101 sequentially output shift pulses Vs1 to Vsn having a pulse width equal to a cycle of the horizontal clocks HCK and HCKX. The shift pulses Vs1 to Vsn are supplied to switches 102-1 to 102-n of the clock extracting switch group 102.
The switches 102-1 to 102-n of the clock extracting switch group 102 are alternately connected at one terminal thereof to clock lines 104-1 and 104-2 that input the horizontal clocks HCKX and HCK. By being supplied with the shift pulses Vs1 to Vsn from the shift stages of the shift register 101, the switches 102-1 to 102-n of the clock extracting switch group 102 are sequentially turned on to sequentially extract the horizontal clocks HCKX and HCK. The extracted pulses are supplied as sampling pulses Vh1 to Vhn to switches 103-1 to 103-n of the sampling switch group 103.
The switches 103-1 to 103-n of the sampling switch group 103 are each connected at one terminal thereof to a video line 105 for transmitting a video signal “video”. The switches 103-1 to 103-n of the sampling switch group 103 are sequentially turned on in response to the sampling pulses Vh1 to Vhn extracted and sequentially supplied by the switches 102-1 to 102-n of the clock extracting switch group 102, thereby sample the video signal “video”, and then supply the sampled video signal. “video” to signal lines 106-1 to 106-n of a pixel array unit (not shown).
In the clock driving type horizontal driving circuit 100 according to the foregoing conventional example, a delay is caused in the sampling pulses Vh1 to Vhn by wiring resistance, parasitic capacitance, and the like in a transmission process from the extraction of the horizontal clocks HCKX and HCK by the switches 102-1 to 102-n of the clock extracting switch group 102 to the supply of the horizontal clocks HCKX and HCK as the sampling pulses Vh1 to Vhn to the switches 103-1 to 103-n of the sampling switch group 103.
The delay in the sampling pulses Vh1 to Vhn in the transmission process causes waveforms of the sampling pulses Vh1 to Vhn to be rounded. As a result, directing attention to the sampling pulse Vh2 in the second stage, for example, as is particularly clear from a timing chart of FIG. 10, the waveform of the sampling pulse Vh2 in the second stage overlaps the waveforms of the preceding and succeeding sampling pulses Vh1 and Vh3 in the first stage and the third'stage.
In general, as shown in FIG. 10, charge and discharge noise is superimposed on the video line 105 at an instant when each of the switches 103-1 to 103-n of the sampling switch group 103 is turned on, because of a relation in potential between the video line 105 and the signal lines 106-1 to 106-n.
In such a situation, when the sampling pulse Vh2 overlaps the sampling pulses in the preceding and succeeding stages, as described above, charge and discharge noise caused by turning on the sampling switch 103-3 in the third stage is sampled in sampling timing of the second stage based on the sampling pulse Vh2. The sampling switches 103-1 to 103-n sample and hold the potential of the video line 105 in timing in which the sampling pulses Vh1 to Vhn reach an “L” level.
In this case, since the charge and discharge noise superimposed on the video line 105 is varied and also the timing in which each of the sampling pulses Vh1 to Vhn reaches the “L” level is varied, the potential sampled by the sampling switches 103-1 to 103-n is varied. As a result, the variation in the sampled potential appears as a vertical streak on the display screen, thus degrading picture quality.
When the number of pixels in a horizontal direction, in particular, is increased with higher definition in the active matrix liquid crystal display apparatus of the dot-sequential driving type, it is difficult to secure a sufficient sampling time for the sequential sampling for all the pixels of the video signal “video” inputted by one system within a limited horizontal effective period. Accordingly, in order to secure a sufficient sampling time, as shown in FIG. 11, a method is used in which video signals are inputted in parallel by m systems (m is an integer of 2 or more), and with m pixels in the horizontal direction as a unit, m sampling switches are provided and driven simultaneously by one sampling pulse, whereby sequential writing in units of m pixels is performed.
With such a method of simultaneously driving a plurality of pixels, a ghost tends to occur when sampling pulses overlap each other as described above. The ghost refers to an undesired interference image displaced from and overlapping a normal image. The conventional driving method that may cause the overlapping has a small ghost margin.
As described above, the active matrix display apparatus of the dot-sequential type conventionally has problems of the vertical streak defect and the insufficient ghost margin. Accordingly, in order to eliminate the vertical streak and increase the ghost margin, a non-overlap sampling method is disclosed in Japanese Patent Laid-Open No. 2002-072987. FIGS. 12A and 12B are a circuit diagram showing an example of a display apparatus using the non-overlap sampling method and a waveform chart. As shown in FIG. 12A, the display apparatus includes a pixel array unit, a vertical driving circuit 16, and a horizontal driving circuit 17. The pixel array unit includes gate lines 13 in a form of rows, signal lines 12 in a form of columns, and pixels 11 arranged in a form of a matrix at intersections of the gate lines 13 and the signal lines 12. The vertical driving circuit 16 is connected to the gate lines 13 to sequentially select rows of the pixels 11. The horizontal driving circuit 17 is connected to the signal lines 12. The horizontal driving circuit 17 operates on the basis of a predetermined clock signal to sequentially write a video signal to pixels 11 of a selected row. In this example, the video signal is divided into two systems video-a and video-b; thus, a two-pixel simultaneous driving method is used.
The horizontal driving circuit 17 includes a shift register 21, a shaping switch group 22, and a sampling switch group 23. The shift register 21 performs shift operation in synchronism with externally inputted clock signals to sequentially output a shift pulse from each of shift stages thereof. The shaping switch group 22 shapes the shift pulses sequentially outputted from the shift register 21 to sequentially output non-overlapping sampling pulses Vh1 and Vh2 temporally separated from each other. In the example shown in FIG. 12A, the sampling pulse Vh1 is outputted from an N stage and the sampling pulse Vh2 is outputted from a next N+1 stage. In response to the sampling pulses Vh1 and Vh2, the sampling switch group 23 sequentially samples the input video signals video-a and video-b in a non-overlapping manner. The sampling switch group 23 then supplies the sampled video signals video-a and video-b to the signal lines 12. In the example shown in FIG. 12A, a sampling switch 23-1 samples the video signals video-a and video-b in response to the sampling pulse Vh1 and supplies the sampled video signals video-a and video-b to two signal lines (1) and (2), respectively. A next sampling switch 23-2 operates in response to the sampling pulse Vh2 to sample the video signals video-a and video-b and supply the sampled video signals video-a and video-b to signal lines (3) and (4), respectively.
However, a new picture quality defect is caused by the introduction of this non-overlap sampling driving. This will be briefly described with reference to FIG. 12B. As shown in the figure, the sampling pulse Vh1 outputted from the N stage and the sampling pulse Vh2 outputted from the next N+1 stage are temporally separated from each other, thus enabling non-overlap sampling. In response to the sampling pulse Vh1, the video signal video-b is sampled and supplied to the signal line (2). The potential of the signal line (2) is represented as Vsig1-b in the waveform chart. In response to the next sampling pulse Vh2, the video signal video-a is sampled and supplied to the third signal line (3). The potential change of the signal line (3) is represented as Vsig2-a.
It is generally known that a parasitic capacitance exists between adjacent signal lines. In FIG. 12A, a parasitic capacitance between signal lines is denoted by C. A capacitance of each signal line is denoted by Csig. In non-overlap sampling, the potential Vsig1-b of the signal line (2) in the preceding stage is held first, and thereafter the input video signal video-a is written to the signal line (3) in the succeeding stage. At this time, capacitive coupling is introduced from the signal line (3) in the succeeding stage to the signal line (2) in the preceding stage via the parasitic capacitance C between the signal lines, whereby a vertical streak occurs. Letting ΔV be the potential change of the signal line (2) in the preceding stage, which potential change is caused by the capacitive coupling, and ΔVsig be the potential written to the signal line (3) in the succeeding stage, the potential variation causing the vertical streak is expressed as ΔV=C·ΔVsig/(C+Csig). As is clear from this equation, the greater the potential difference written to each signal line, the greater the potential variation ΔV caused by coupling between the signal lines. Of course, the larger the parasitic capacitance C between the signal lines, the greater the potential variation ΔV.
FIG. 13 schematically shows the new picture quality defect caused by introducing non-overlap sampling driving. In the example shown in FIG. 13, six-pixel simultaneous driving is performed, and therefore non-overlap sampling is performed with six columns of pixels 11 taken as one unit. At each unit boundary portion of the multistage-connected shift register, a potential jump occurs via a parasitic capacitance between adjacent signal lines, resulting in a vertical streak in a one-pixel column of each unit. Because of a mechanism of occurrence of the vertical streak, the vertical streak is caused between adjacent signal lines at a boundary between units. As viewed from a direction of horizontal scanning, a potential jump occurs into the signal line in the preceding stage from the signal line in the succeeding stage via a parasitic capacitance. Thus, as shown in FIG. 13, when pixels 11 are scanned from the left to the right, a picture quality defect referred to as a vertical streak occurs in a rightmost pixel column of each unit. When the pixel array unit 15 is scanned from the right to the left, on the other hand, a vertical streak appears in a leftmost pixel column of each unit. This vertical streak defect cannot be completely eliminated even when the potential of each signal line is adjusted in advance by a precharge signal, thus presenting a problem to be solved.